The present invention relates, in general, to integrated circuit memories. More particularly, the present invention relates to a circuit and method for refreshing the memory cells in the integrated circuit memory.
Efforts have been made to reduce the power consumption of integrated circuit dynamic memories (“DRAMs”). One area of attention for reducing the power required is in the refresh circuitry for the memory array in the DRAM.
Referring now to FIG. 1, a block diagram is shown of a typical refresh control circuit for DRAM integrated circuits to perform “regular” (unmasked) refreshes. An unmasked refresh is also known as “self-refresh”, “auto-refresh” or “CBR” refresh (CAS Before RAS). The refresh control circuit 10 shown in FIG. 1 is made up of RILATH blocks 18 or address buffers (Row Input Latch). Each row address uses either external inputs for non-refresh cycles (BAA<0>, BAA<1>, . . . , BAA<7> are shown in FIG. 1) or refresh counter inputs (RAIB<11:0> in this figure) for refresh cycles. The row address input is controlled by the REFCLK signal generated by the refresh control circuit 12. The address buffers 18 then output row addresses to row predecoders and row decoders (BAAB<0,1> . . . RAB<7> in FIG. 1) as is known in the art. The blocks 16 labeled REFBIT<0>, REFBIT<1> and REFBIT<11> are refresh counters. Refresh counters 16 interface with the INC increment logic block 14 that monitors the current state of the refresh counter or refbits (BAAINC<0> through RAINC<11>) and outputs information (INC<1:11>) that tells instructs the refbits to increment or not for the next refresh address. The refresh control circuit 12 uses the precharge bar signal (PREB), refresh bar signal (REFB) and clock signal (MCLK) external inputs to control the refresh counter blocks and with the REFINCB and REFOUT signals. The REFOUT signal is also used to force the chip into an active state through the ACTLATCH circuit (not shown in FIG. 1) when refreshing.
One technique designers have used to reduce refresh power is to not refresh the entire array as would be done in the circuit of FIG. 1. Instead, addresses are loaded into a register prior to any refresh cycles selecting only a portion of the array. For example, only the first half or quarter of the memory array that the particular application happens to be using at the time is refreshed. This way ½ or ¾ of the refresh power could be saved. The problem with this approach is that the controller needs to know in advance which portions of the DRAM needs to be refreshed and which portions do not. Another problem with this approach is that there is little flexibility in refreshing subarrays within the memory array. The most significant addresses are typically used to choose the first half, quarter, eighth or sixteenth of the array for refreshing. If the active part of the array is in the last sixteenth of the array then the entire memory array must be active for refresh and no power is saved.
This prior art refresh technique is typically applied to self-refresh modes and not to CBR or auto-refresh modes or cycles, (or standard refresh cycles).
In the prior art refresh technique described above the portions of the memory to be refreshed or not refreshed need to be known in advance and stored in a register with a special mode register set command cycle. Little flexibility is available on choosing which subarrays to refresh and which to mask from refreshing. The prior art technique requires that the arrays that are masked from refresh are contiguous. That is, these masked arrays are one-half, one-fourth, one-eighth, etc., of the original array. Typically a factor of two portion of the array is being masked that has adjacent physical and/or electrical addressing.
What is desired, therefore, is a novel refresh technique that does not require that advance knowledge of the subarrays to be refreshed and provides more flexibility in refreshing non-contiguous subarrays in the memory.